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CY7C346
128-Macrocell MAX(R) EPLD
Features
* 128 macrocells in eight logic array blocks (LABs) * 20 dedicated inputs, up to 64 bidirectional I/O pins * Programmable interconnect array * 0.8-micron double-metal CMOS EPROM technology * Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346 are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C346 allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346 allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C346 reduces board space, part count, and increases system reliability.
Functional Description
The CY7C346 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX(R) architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions.
Logic Block Diagram
.. 1 . 78 . 79 80 . 83 . 84 .. 2 .. 5 .. 6 .. 7 (C7) [16] (A10) [9] (B9) [10] (A9) [11] (A8) [14] (B7) [15] (A7) [17] (C6) [20] (A5) [21] (B5) [22] . INPUT/CLK ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT ..... INPUT SYSTEM CLOCK LAB A MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121-128 LAB G MACROCELL 104 MACROCELL 103 MACROCELL 102 MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 P I A MACROCELL 105-112 LAB F MACROCELL 88 MACROCELL 87 MACROCELL 86 MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 86-96 LAB E 49 50 51 52 53 54 55 56 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 72 71 70 69 68 67 66 65 [58] [57] [56] [55] [54] [53] [52] [51] (M4) NC (N3) NC (M3) 55 (N2) 54 (M2) 53 (N1) 52 (L2) 51 (M1) 50 INPUT [59] INPUT [60] INPUT [61] INPUT [64] INPUT [65] INPUT [66] INPUT [67] INPUT [70] INPUT [71] INPUT [72] (N4) (M5) (N5) (N6) (M7) (L7) (N7) (L8) (N9) (M9) . . . . . . . . . . 36 37 38 41 42 43 44 47 48 49
8 (B13) [1] 9 (C12) [2] 10 (A13) [3] 11 (B12) [4] 12 (A12) [5] 13 (11) [6] NC (A11) [7] NC (B10) [8]
1 2 3 4 5 6 7 8
[100] (C13) NC [99] (D12) NC [98] (D13) 77 [97] (E12) 76 [96] (E13) 75 [95] (F11) 74 [92] (G13) 73 [91] (G11) 72
MACROCELL 9-16 LAB B MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
14 (A4) 15 (B4) 16 (A3) 17 (A2) 18 (B3) 21 (A1) NC (B2) NC (B1)
[23] [24] [25] [26] [27] [28] [29] [30]
17 18 19 20 21 22 23 24
[90] [89] [86] [85] [84] [83] [82] [81]
(G12) NC (H13) NC (J13) 71 (J12) 70 (K13) 69 (K12) 68 (L13) 67 (L12) 64
MACROCELL 25-32 LAB C MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
22 (C2) [31] 25 (C1) [32] 26 (D2) [33] 27 (D1) [34] 28 (E2) [35] 29 (E1) [36] NC (F1) [39] NC (G2) [40]
33 34 35 36 37 38 39 40
[80] [79] [78] [77] [76] [75] [74] [73]
(M13) (M12) (N13) (M11) (N12) (N11) (M10) (N10)
NC NC 63 60 59 58 57 56
MACROCELL 41-48 LAB D 30 (G3) [41] 31 (G1) [42] 32 (H3) [45] 33 (J1) [46] 34 (J2) [47] 35 (K1) [48] NC (K2) [49] NC (L1) [50] MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
MACROCELL 57- 64 3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) 16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [18, 19, 43, 44, 68, 69, 93, 94] [12, 13, 37, 38, 62, 63, 87, 88] VCC GND
MACROCELL 73- 80 () - PERTAIN TO 100-PIN PGA PACKAGE [ ] -PERTAIN TO 100-PIN PQFP PACKAGE
Cypress Semiconductor Corporation Document #: 38-03005 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 19, 2004
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Selection Guide
7C346-25 Maximum Access Time Maximum Operating Current Commercial Military Industrial Maximum Standby Current Commercial Military Industrial 25 250 325 320 225 275 275 7C346-30 30 250 320 320 225 275 275 7C346-35 35 250 320 320 225 275 275
CY7C346
Unit ns mA
mA
Pin Configurations
PLCC/CLCC Top View
INPUT/CLK INPUT INPUT INPUT V CC V CC INPUT INPUT INPUT INPUT INPUT INPUT GND GND
PGA Bottom View
I/O I/O I/O
I/O I/O I/O I/O
11 10 9 8 7 6 I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O
N M L K J H G F E D C B A
I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O
I/O I/O
INP I/O
INP INP INP VCC INP INP GND INP VCC INP GND INP INP
I/O I/O
I/O I/O
I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O 13
VCC VCC I/O I/O
I/O I/O
GND GND
CY7C346
I/O I/O
I/O VCC I/O I/O
CY7C346
63 62 61 60 59 58 57 56 55
I/O GND GND I/O I/O I/O I/O I/O 1 I/O I/O I/O I/O I/O 2 I/O I/O 3 I/O I/O 4 INP INP GND /CLK I/O
I/O I/O I/O 11 I/O I/O 12
INP VCC INP GND INP INP VCC INP 5 6 7
54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INPUT GND GND INPUT INPUT INPUT INPUT INPUT INPUT V CC V CC INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O
INP INP INP 8 9 10
Document #: 38-03005 Rev. *B
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Pin Configurations (continued)
PQFP Top View
GND VCC GND CC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V I/O I/O
CY7C346
100 99 98 97 96 95 94 93 92 91 90 89 88 I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT GND GND INPUT INPUT INPUT/CLK INPUT VCC VCC INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
87 86 85 84 83
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT VCC VCC INPUT INPUT INPUT INPUT GND GND INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O
CY7C346
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
Document #: 38-03005 Rev. *B
VCC
I/O
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Logic Array Blocks
There are eight logic array blocks in the CY7C346. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C346 provides 20 dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins
CY7C346
that may be individually configured for input, output, or bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device.
Timing Delays
Timing delays within the CY7C346 may be easily determined using Warp(R), Warp ProfessionalTM, or Warp EnterpriseTM software. The CY7C346 has fixed internal delays, allowing the user to determine the worst case timing delays for any design.
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tCLR tLAC tPRE INPUT DELAY tIN LOGIC ARRAY DELAY tLAD tRSU tRH
REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX
INPUT
SYSTEM CLOCK DELAY tICS CLOCK DELAY tIC FEEDBACK DELAY tFD
PIA DELAY tPIA
I/O DELAY tIO
Figure 1. CY7C346 Internal Timing Model
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C346 contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND (VIN or VOUT) VCC. Unused inputs must always be tied to an appropriate logic level Document #: 38-03005 Rev. *B
(either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have.
Design Security
The CY7C346 contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be Page 4 of 21
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obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. The CY7C346 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.
CY7C346
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on dedicated input pins. The parameter tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAWL) is less than 1/(tAS2 + tAH). When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration.
Typical ICC vs. fMAX
400
ICC ACTIVE (mA) Typ.
300
VCC = 5.0V Room Temp.
200
100
0 100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same asynchronous clock as the CY7C346. In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device's register.
100 IOL 80 60 40 IOH 20 VCC = 5.0V Room Temp.
0
0.45
1
2
3
4
5
VO OUTPUT VOLTAGE (V)
Document #: 38-03005 Rev. *B
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to+150C Ambient Temperature with Power Applied............................................. -55C to+125C Maximum Junction Temperature (under bias).................................................................. 150C Supply Voltage to Ground Potential ............... -2.0V to +7.0V Maximum Power Dissipation...................................2500 mW DC VCC or GND Current ............................................500 mA
CY7C346
DC Output Current per Pin ...................... -25 mA to +25 mA DC Input Voltage[1] .........................................-3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage........................................... > 1100V (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature 0C to +70C -40C to +85C -55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[2]
Parameter Description VOH Output HIGH Voltage VOL VIH VIL IIX IOZ IOS ICC1 ICC2 tR tF Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current[5] Recommended Input Rise Time Recommended Input Fall Time Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -10 -40 -30 Min. 2.4 Max. 0.45 VCC + 0.3 0.8 +10 +40 -90 225 275 250 320 100 100 Unit V V V V A A mA mA mA ns ns
GND < VIN < VCC VO = VCC or GND VCC = Max., VOUT = 0.5V[3, 4] VI = GND (No Load) Commercial Military/Industrial VI = VCC or GND (No Load) Commercial f = 1.0 MHz[4] Military/Industrial
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2V, f = 1.0 MHz VOUT = 2V, f = 1.0 MHz Max. 10 20 Unit pF pF
AC Test Loads and Waveforms[6]
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: R2 250 R1 464 5V OUTPUT 5 pF R2 250 R1 464 ALL INPUT PULSES 3.0V 10% GND 6 ns 90% 90% 10% 6 ns
INCLUDING JIG AND SCOPE (a) (b) THEVENIN EQUIVALENT (Commercial/Military) 163 OUTPUT 1.75V
Notes: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -3.0V for periods less than 20 ns. 2. Typical values are for TA = 25C and VCC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed by design but not 100% tested. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
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7C346-25 Min. Max. 25 40 37 52 25 25 14 30 15 30 0 8 8 25 25 25 25 25 25 3 16 34.5 55.5 62.5 62.5 3 20 27.7 43.4 50 50 3 30 30 30 3 20 36 0 10 10 30 30 30 35 35 7C346-30 Min. Max. 30 45 44 59 30 30 16 35 25
CY7C346
7C346-35 Min. Max. 35 55 55 75 35 35 20 42
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
Parameter Description tPD1 Dedicated Input to Combinatorial Output Delay[7] tPD2 I/O Input to Combinatorial Output Delay[10] tPD3 Dedicated Input to Combinatorial Output Delay with Expander Delay[11] tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[4, 12] tEA Input to Output Enable Delay[4, 7] tER Input to Output Disable Delay[4, 7] tCO1 Synchronous Clock Input to Output Delay tCO2 Synchronous Clock to Local Feedback to Combinatorial Output[4, 13] tS1 Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 14] tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] tH Input Hold Time from Synchronous Clock Input[7] tWH Synchronous Clock Input HIGH Time tWL Synchronous Clock Input LOW Time tRW Asynchronous Clear Width[4, 7] tRR Asynchronous Clear Recovery Time[4, 7] tRO Asynchronous Clear to Registered Output Delay[7] tPW Asynchronous Preset Width[4, 7] tPR Asynchronous Preset Recovery Time[4, 7] tPO Asynchronous Preset to Registered Output Delay[7] tCF Synchronous Clock to Local Feedback Input[4, 15] tP External Synchronous Clock Period (1/(fMAX3)[4] fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 16] fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 17] fMAX3 Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 18] fMAX4 Maximum Register Toggle Frequency (1/(tWL + tWH)[4, 19] tOH Output Data Stable Time from Synchronous Clock Input[4, 20] Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz ns
45 0 12.5 12.5 35 35 35
35 6 25 22.2 32.2 40 40 3
Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. 8. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. 9. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 10. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 11. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. 12. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 13. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 14. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. 15. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 16. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs. 17. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local originating within the same LAB. 18. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation. 19. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to the dedicated clock input pin. 20. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
Document #: 38-03005 Rev. *B
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CY7C346
Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-25 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input to Output Delay[7] Asynchronous Clock Input to Local Feedback to Combinatorial Output[20] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] I/O Input Set-Up Time to Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time Asynchronous Clock Input LOW
[7]
7C346-30 Min. Max. 30 46 6 22 8 14 11
7C346-35 Min. Max. 35 55 8 28 10 16 14 Unit ns ns ns ns ns ns ns 22 30 23.2 33.3 28.5 33.3 15 ns ns MHz MHz MHz MHz ns
Min.
Max. 25 39
5 19 6 11 9 15 20 33.3 50
Time[7, 21] Input[4, 22]
Asynchronous Clock to Local Feedback
18 25 27.7 40 33.3 40 15
External Asynchronous Clock Period (1/(fMAXA4))[4] External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4, 23] Maximum Internal Asynchronous Frequency[4, 24] Data Path Maximum Frequency in Asynchronous Mode[4, 25] Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 26] Output Data Stable Time from Asynchronous Clock Input[4, 27]
40 50 15
Notes: 21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path. 24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(tAWH + tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single LAB. This parameter is tested periodically by sampling production material. 25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the lesser of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin.
Document #: 38-03005 Rev. *B
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USE ULTRA37000TM FOR ALL NEW DESIGNS
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay
[28]
CY7C346
7C346-30 Min. Max. 7 6 14 14 12 5 11 11 8 8
7C346-35 Min. Max. 9 9 20 16 13 6 13 13 10 10 Unit ns ns ns ns ns ns ns ns ns ns 4 2 4 12.5 12.5 ns ns ns ns ns 18 1 2 7 7 7 7 ns ns ns ns ns ns ns 20 ns
Min.
Max. 5 6 12 12 10 5 10 10
Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow Through Latch Delay Register Delay Transparent Mode Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset and Clear Pulse Width Asynchronous Preset and Clear Recovery Time Programmable Interconnect Array Delay Time 5 5 Delay[29] 8 8 6 6
3 1 3 10 10 14 1 1 5 5 6 6 14
4 2 4
16 1 1 6 6
16
Notes: 28. Sample tested only for an output change of 500 mV. 29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
Document #: 38-03005 Rev. *B
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Military External Synchronous Switching Characteristics[6] Over Operating Range
7C346-30 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS1 tS2 tH tWH tWL tRW tRR tRO tPW tPR tPO tCF tP fMAX1 fMAX2 fMAX3 fMAX4 tOH Description Dedicated Input to Combinatorial Output Delay I/O Input to Combinatorial Output Delay[10] Dedicated Input to Combinatorial Output Delay with Expander Delay[11] I/O Input to Combinatorial Output Delay with Expander Delay[4, 12] Input to Output Enable Delay[4, 7] Input to Output Disable Delay[4, 7] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[4, 13] Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7, 14] I/O Input Set-Up Time to Synchronous Clock Input[7] Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Asynchronous Clear Width[4, 7] Time[4, 7] Asynchronous Clear Recovery Asynchronous Preset 20 36 0 10 10 30 30 30 30 Time[4, 7 ] 30 30 3 20 27.7 43.4 50 50 3 25 22.2 32.2 40 40 3 35 35
[7]
CY7C346
7C346-35 Min. Max. 35 55 55 75 35 35 20 42 25 45 0 12.5 12.5 35 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 6 ns ns ns MHz MHz MHz MHz ns
Min.
Max. 30 45 44 59 30 30 16 35
Asynchronous Clear to Registered Output Delay[7] Width[4, 7] Asynchronous Preset Recovery
Asynchronous Preset to Registered Output Delay[7] Synchronous Clock to Local Feedback Input[4, 15] External Synchronous Clock Period (1/(fMAX3 External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 16] Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 17] Data Path Maximum Frequency, lesser of (1/(tWL + tWH)), (1/(tS1 + tH)) or (1/tCO1)[4, 18] Maximum Register Toggle Frequency (1/(tWL + tWH))[4, 19] Output Data Stable Time from Synchronous Clock Input[4, 20] ))[4]
Document #: 38-03005 Rev. *B
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Military External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-30 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input to Output Delay
[7]
CY7C346
7C346-35 Min. Max. 35 55 8 28 10 16 14 Unit ns ns ns ns ns ns ns 22 30 23.2 33.3 28.5 33.3 15 ns ns MHz MHz MHz MHz ns
Min.
Max. 30 46
Asynchronous Clock Input to Local Feedback to Combinatorial Output[20] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] I/O Input Set-Up Time to Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input LOW Time[7, 21] Input[4, 22] ))[4] 25 27.7 40 33.3 40 15 Asynchronous Clock to Local Feedback 6 22 8 14 11
18
External Asynchronous Clock Period (1/(fMAXA4 External Feedback Maximum Frequency in Asynchronous Mode (1/(tACO1 + tAS1))[4, 23]
Maximum Internal Asynchronous Frequency[4, 24] Data Path Maximum Frequency in Asynchronous Mode[4, 25 ] Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 26] Output Data Stable Time from Asynchronous Clock Input[4, 27]
Document #: 38-03005 Rev. *B
Page 11 of 21
USE ULTRA37000TM FOR ALL NEW DESIGNS
Military Typical Internal Switching Characteristics Over Operating Range
7C346-30 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay
[28]
CY7C346
7C346-35 Min. Max. 9 9 20 16 13 6 13 13 10 10 Unit ns ns ns ns ns ns ns ns ns ns 4 2 4 12.5 12.5 ns ns ns ns ns 18 3 2 7 7 7 7 ns ns ns ns ns ns ns 20 ns
Min.
Max. 7 6 14 14 12 5 11 11
Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow Through Latch Delay Register Delay Transparent Mode Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset and Clear Pulse Width Asynchronous Preset and Clear Recovery Time Programmable Interconnect Array Delay Time 6 6 Delay[29] 10 10 8 8
4 2 4
16 2 1 6 6
16
Document #: 38-03005 Rev. *B
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Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1 COMBINATORIAL OUTPUT tER[7] COMBINATORIAL OR REGISTERED OUTPUT tEA [7] HIGH-IMPEDANCE THREE-STATE VALID OUTPUT
[7]
CY7C346
/tPD2
[10]
HIGH-IMPEDANCE THREE-STATE
External Synchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK [7] SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] tOH tRO/tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [7] tRW/tPW tRR/tPR
tS1
tH
tWH
tWL
External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL
tACO1 tAOH
tRW/tPW
tRR/tPR
ASYNCHRONOUS CLEAR/PRESET
tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK
Document #: 38-03005 Rev. *B
Page 13 of 21
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Switching Waveforms (continued)
Internal Combinatorial
tIN INPUT PIN tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
CY7C346
LOGIC ARRAY OUTPUT
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tRH tAWH tAWL tF
Internal Synchronous
tCH SYSTEM CL OCK PIN tIN SYSTEM CL OCK AT REGISTER tRSU DATA FROM LOGIC ARRAY tRH tICS tCL
Document #: 38-03005 Rev. *B
Page 14 of 21
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Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM LOGIC ARRAY
CY7C346
tRD
tOD
DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE
Document #: 38-03005 Rev. *B
Page 15 of 21
USE ULTRA37000TM FOR ALL NEW DESIGNS
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC1 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups
CY7C346
Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tS1 tS2 tH tWH tWL tRO tPO tACO1 tACO2 tAS1 tAH tAWH tAWL Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Ordering Information
Speed (ns) 25 Ordering Code CY7C346-25HC/HI CY7C346-25JC/JI CY7C346-25NC/NI CY7C346-25RC/RI CY7C346-30HC/HI CY7C346-30JC/JI CY7C346-30NC/NI CY7C346-30HMB CY7C346-30RMB Package Name H84 J83 N100 R100 H84 J83 N100 H84 R100 Package Type 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Pin Grid Array Operating Range Commercial/Industrial
30
Commercial/Industrial
Military
Document #: 38-03005 Rev. *B
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USE ULTRA37000TM FOR ALL NEW DESIGNS
Ordering Information (continued)
Speed (ns) 35 Ordering Code CY7C346-35JC/JI CY7C346-35NC/NI CY7C346-35RC/RI CY7C346-35HMB CY7C346-35RMB Package Name J83 N100 R100 H84 R100 Package Type 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Pin Grid Array 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Pin Grid Array
CY7C346
Operating Range Commercial/Industrial
Military
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081-**
Document #: 38-03005 Rev. *B
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Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
CY7C346
51-85006-*A
Document #: 38-03005 Rev. *B
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USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
CY7C346
51-85052-*A
Document #: 38-03005 Rev. *B
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USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams (continued)
100-Pin Windowed Ceramic Pin Grid Array R100
CY7C346
51-80010-*C
MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-03005 Rev. *B
Page 20 of 21
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR ALL NEW DESIGNS
Document History Page
Document Title: CY7C346 128-Macrocell MAX(R) EPLD Document Number: 38-03005 REV. ** *A *B ECN NO. 106270 113614 213375 Issue Date 04/23/01 04/11/02 See ECN Orig. of Change SZV OOR FSG Description of Change Change from Spec number 38-00244 to 38-03005 PGA package diagram dimensions updated
CY7C346
Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03005 Rev. *B
Page 21 of 21

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